Avalanche Photodiodes (APDs) are photodetectors that use avalanche multiplication to achieve internal gain. Many prior art sources describe photodetectors, such as J. C. Campbell, “Recent Advances in Telecommunications Avalanche Photodiodes,” J. Lightwave Technology v. 25(1) Pp. 109-121 (2007), which are hereby incorporated by reference. Single photon avalanche photodiodes (SPADs) are a specific class of avalanche photodiodes that are capable of detecting single photons. Examples of SPADs are given for example in S. Cova, et al., “Evolution and prospects for single-photon avalanche diodes and quenching circuits,” J. Modern Optics v. 51(9-10) Pp. 1267-1288 (2004), which is hereby incorporated by reference.
APD and SPAD arrays are also known in the art, and include a range of devices such as the silicon photomultiplier (SiPM), the multi-pixel photon detector (MPPC), and a number of similar devices. Reference is made to the digital SiPM (dSiPM) approach disclosed in US Pub. Nos. 2011/0079727, 2010/0127314, and T. Frach et al. “The Digital Silicon Photomultiplier—System Architecutre and Performance Evaluation,” 2010 IEEE Nuclear Science Symposium Conference Record (NSS/MIC), Pp. 1722-1727 (2010), which are hereby incorporated by reference. Other examples of prior devices are described in International Workshop on New Photon-detectors 2012, LAL Orsay, France, and the presentation entitled “The SiPM Physics and Technology—a Review—,” G. Collazuol, found online at the time of this submission at http://indico.cern.ch/getFile.py/access?contribId=72&resId=0&materialId=slides &confId=164917; W-S Sul et al. “Guard Ring Structures for Silicon Photomultipliers,” IEEE Electron; Dev., Lett, v.31(1) Pp 41-43 (2010); A. G. Stewart et al. “Performance of 1-mm2 Silicon Photomultiplier,” IEEE J. Quantum Electronics Vol. 44(2) pp. 157-164, (2008), all of which are hereby incorporated by reference. A simple SPAD array devices incorporates a single photon avalanche diode (SPAD) and a passive quench circuit. The passive quench circuit consists of a current limiting element (usually a resistor) in parallel with a bypass capacitor as described in S. Tiza et al. “Electronics for single photon avalanche diode arrays,” Sensors and Actuators A 140, Pp. 113-122 (2007) and S. Seifert et al. “Simulation of Silicon Photomultiplier Signals,” IEEE Trans. Nuclear Science, v. 56(6) Pp. 3726-3733 (December 2009). All of the above references are incorporated herein by references.
Prior art APD arrays have also used various techniques for isolating adjacent APD elements. For example PN junction isolation and mesa isolation are well known in the prior art. PN junction isolation is generally achieved by confining the lateral extent of doping to separate p-type regions (on an n-type substrate) or n-type regions (on a p-type substrate) or both. Edge effects in isolated devices often results in electrical field crowding along the perimeter of the APD device, which would normally cause a non-uniform avalanche gain profile. Edge effects in isolated devices are mitigated through the use of double-diffused structures, guard ring structures, or other approaches well known in the state of the art (see, for example, Y. Liu, S. R. Forrest, J. Hladky, M. J. Lange, G. H. Olsen, and D. E. Ackley, “A Planar InP/InGaAs Avalanche Photodiode with Floating Guard Ring and Double Diffused Junction,” J. Lightwave Technology, v. 10(2) February 2991, and Chapter 3: Breakdown Voltage in Power Semiconductor Devices, Pp. 67-127 by B. J. Baliga, PWS Publishing Company, Boston, Mass. 1996).
Mesa isolation can be used to define the active area of a APD and to laterally isolate adjacent APD elements, by partially or fully removing the conductive pathway between adjacent APD elements. The use of a beveled edge structure in mesa isolation can be used to mitigate edge effects, but places stringent demands on the mesa structure (bevel angle) and surface state density of the mesa. Beveled edge mesa structures are described in detail by B. J. Baliga “Power Semiconductor Devices,” Pp. 103-111, PWS Publishing Company, Boston, Mass., which is hereby incorporated by reference.
Ion implantation isolation is used to render a semiconductor region insulating, semi-insulating, or very low conductivity. Ion implantation isolation is often used with respect to compound semiconductor devices where ion implantation creates a sufficient amount of deep levels in a semiconductor region to compensate some of the doping in said semiconductor region, thereby reducing conductivity and often rendering the region highly resistive. For all cases of ion implantation isolation, a residual conductivity remains, with experimental values often exceeding 1E9 ohms/square, though lower values of resistivity are also common. The residual conductivity is often attributed to residual free carrier conductivity and/or hopping conduction. For semiconductors such as Si, SiGe, SiC, GaAs, AlGaAs, GaInP, InGaAsP, InGaAlAs, and InAlInN, implant isolation is often achieved by using hydrogen ions, helium ions, oxygen ions, nitrogen ions, boron ions, fluorine ions, arsenic ions, and phosphorous ions, through those skilled in the art will recognize that any suitable ion may be used. The residual conductivity is a function of the implant species, implant energy, implant dose, implant profile, and semiconductor material. While conventional ion implantation for doping generally achieves (at most) 1 free carrier for each dopant atom, ion implantation isolation often achieves a multiplier effect whereby implantation of a single atom (or species) can produce a 10-fold or higher reduction in the free carrier concentration. This occurs because the lattice damage induced by the implanted ion produces the compensating donors/acceptors, and not the specific ion itself. In some cases, the specific ion may also be used as a compensating level, such as through the use of arsenic implantation in GaAs. Ion implant isolation is well known in the literature, as illustrated by one or more of the following references: Q. Zhou, et al. “Proton-Implantation-Isolated 4H—SiC Avalanche Photodiodes,” IEEE Photonics Technology Lett. v. 21(23) Pp. 1734-1736 (2009); I. Sandall, et al. “Planar InAs photodiodes fabricated using He ion implantation,” Optics Express v.20(8) Pp. 8575-8583 (2012); Q. Zhou, et al. “Proton-Implantation-Isolated Separate Absorption Charge and Multiplication 4H—SiC Avalanche Photodiodes,” IEEE Photonics Technology Letters v. 23(5) Pp. 299-301 (2011); G. E. Bulman, et al. “Proton isolated In0.2Ga0.8As/GaAs strained layer superlattice avalanche photodiode,” Appl. Phys. Lett. v.48, Pp. 1015-1017 (1986); I. Danilov, et al. “Electrical isolation of InGaP by proton and helium ion irradiation,” J. Appl. Phys., v. 92 Pp. 4261-4265 (2002); S. J. Pearton, “Ion Implantation for Isolation of III-V Semiconductors,” Materials science reports, v. 4(8), (1990); Vasteras Willy Hermansson, et al. in U.S. Pat. No. 5,914,499, entitled “High Voltage Silicon Carbide Semiconductor device with bended edge” (1999); Tzu-Yu Wang, U.S. Pub. No. 2005/0078725, entitled “Methods for Angled Ion Implantation of Semiconductor Devices, (2005); D. B. Slater, et al., U.S. Pat. No. 7,943,406 “LED Fabrication via ion implant isolation” (2011); and C-T Huang, J-Y Li, and J. C. Sturm, “Implant Isolation of Silicon Two-Dimensional Electron Gases at 4.2K,” IEEE Electron Dev. Lett., v. 34(1), Pp 21-23 (2013).
A physical beveled edge mesa structure can be fabricated on a photodetector as illustrated in FIG. 1. Semiconductor layers 101 and 102 are formed on a semiconductor substrate 100 using techniques known in the art. Layer 101 is an n-type semiconductor layer with a thickness 111. Layer 102 is a p-type semiconductor layer with a thickness 112. The doping density of n-type semiconductor layer 101 is higher than the doping density of p-type semiconductor layer 102, such that the thickness or width 133 of the depletion region on the p-type side of the junction is larger than the thickness or width 134 of the depletion region on the n-type side of the junction. The dashed line 122 represents the edge of the depletion region in the p-type side of the device, while dashed line 121 represents the edge of the depletion region on the n-type side of the device.
With the appropriate choices for the doping densities in layers 101 and 102, and the bevel angle 131, the total depletion layer thickness 132 in the center portion of the device can be made smaller than the total depletion layer thickness 135 at the perimeter of the device, with the net result that the electric field in the center of the device is larger than the electric field along the perimeter of the device, which therefore allows the device performance to be dominated by the bulk properties of the semiconductor in the center of the device, and reduces the dependence of the device performance on the perimeter.
FIG. 2 illustrates a virtual beveled edge mesa sidewall 205, as described in U.S. application Ser. No. 14/257,179, which is assigned to the same assignee as the present application, and is incorporated herein by reference. The geometries and dimensions of the implant isolated semiconductor regions 201B and 202B are chosen to achieve a positive bevel angle 231 between the implanted regions 201B and 202B and the non-implanted regions 201A and 202A as shown in FIG. 2. In this embodiment, the implant isolated semiconductor region is used to entirely confine the lateral extent of the p-type semiconductor region 202A and the n-type semiconductor regions 201A of the virtual beveled edge APD structure. In the shown embodiment, an n-type semiconductor region 201 and a p-type semiconductor region 202 are grown on top of an n-type semiconductor substrate 200. Implant isolation through a beveled mask is used to define the lateral geometry of the implant. Regions 201B and 202B are the implanted volume of layers 201 and 202 respectively, with the isolation implant chosen to compensate the doping of regions 201B and 202B by at least an order of magnitude in some embodiments, and consequently increase the resistivity of regions 201B and 202B in some embodiments by at least an order of magnitude compared to the unimplanted regions 201A and 202A. The thickness of layer 201 is 211 and the thickness of layer 202 is 212. The thickness of the depletion region in the center of the n-type region 201A is 234, while the thickness of the depletion region in the center of n-type region 202A is 233, and the total depletion region thickness in the center of the device is 232, while the thickness of the depletion region along the virtual beveled mesa edge 205 is 235.
Advantages of the virtual beveled edge mesa structure include performance and ease of fabrication. For example, the virtual mesa does not require a physical extension of the mesa above the layers of the device as was required in the prior art of FIG. 1.
FIG. 3 illustrates a side view of a photodetector pixel array 30 represented by pixels 462A and 462B. The array 30 is formed of a n-type semiconductor region 400, a non-intentionally doped region 401, a p-type semiconductor layer 402, a graded doped p-type layer 403, and a heavily doped p-type contacting layer 404. The heavily-doped layer 404 is patterned into regions 404A, which are disposed above each unimplanted region 402A, as described below. The combination of layers 402, 401, and 400 form a PIN diode structure. The pixels 462A, 462B each include a virtual beveled edge structure defined by implanted regions 402B, 403B and unimplanted regions 402A, 403A. A guard contact 461 surrounds the perimeter of the entire array, and provides a means of isolating the pixels of the array from anything in the exterior of the guard ring. A separate anode connection to each device is 402A, and a common cathode contact 450 is disposed below the n-type semiconductor layer 400. Those skilled in the art will recognize that a similar NIP diode can be formed, with separate cathode connections and common anode connections (see US Patent Application Publication No. 2004/0245592 entitled solid state microchannel plate photodetector by Harmon et al., which is herein incorporated by reference).
The connection between each pixel 462A, 462B and the cathode contact 450 can be represented as a SPAD capacitance (CSPAD) 435 and the shunt resistance of the SPAD (RSPAD) 436 disposed in parallel with each other. In general, the SPAD elements are small (e.g., between 1 μm×1 μm to 100 μm×100 μm), and the resulting SPAD capacitance (CSPAD) 435 ranges from about 0.1 fF to 10 pF. Shunt resistance (RSPAD) 436 is typically greater than 10 GOhm, though it depends on the specific semiconductor materials and processing procedures used to form the SPAD element.
FIG. 4 is a circuit diagram of the anode connections to a prior art photodetector pixel array 30′, which can be the photodetector array 30 described above. As illustrated, the anode of each pixel 40 is electrically coupled to output 45 through a parallel RC circuit 41 comprising an optional capacitor 42 and a resistor 43. The optional capacitor 42 represents a capacitor formed using any method, including using a metal-insulator-metal structure with two metal plates separated by an insulator. A parasitic capacitance (Cp) 47 is also formed between pixel 40 and output 45. The resistor 43 represents a discrete resistor connected between pixel 40 and output 45, and is usually achieved through deposition of a highly resistive thin film, such as polysilicon, very thin metal, or thin silicides. A high frequency signal generated by an incident photon passes through the optional capacitor 42 and/or parasitic capacitance 47 (bypassing the resistor 43), thus allowing for high speed output signals.
At the edge of the array is the ring contact 461, which connects the output of each SPAD element 40 to the output 45. The purpose of the ring contact 461 is to provide analog summation of the currents from each SPAD 40 and connection to the output 45, which generally includes a load resistor 46.
One difficulty with the prior art shown in FIG. 4 is the necessity of incorporating a discrete resistor 43 (and optional capacitor 42) for each pixel 40, as well as the need to provide direct electrical connection between resistor 43 and output 45. This necessitates various processing steps (e.g., metal deposition, patterning, dielectric deposition, etc.) to provide ohmic contact to pixel 40, connection between the ohmic contact and resistor 43 (and optional capacitor 42), and connection between each resistor 43 (and optional capacitor 42) and output 45 using interconnect metal lines between each resistor 43 and the output 45. Each contact, resistor, capacitor and connection consumes significant semiconductor real estate and therefore reduces the available semiconductor area for each pixel 40, reducing the optical sensitivity of each pixel 40.
A challenge remains to fabricate effective avalanche photodetector devices, which have favorable performance and scalability yet have favorable signal detectability. This disclosure addresses and remedies these and other failings of the prior art physical mesa photodetectors and similar devices.